1. Field of the Invention
The present invention relates to a power supply voltage control circuit operative at the time of gradually increasing the value of turning on power. It particularly relates to a power supply voltage control circuit that is applied to a FeRAM having a ‘TC unit’ series-connected memory cell, hereinafter called as ‘chain FeRAM’, or that is applied to a FeRAM having a plurality of DRAM type memory cells, hereinafter called as ‘FeRAM having DRAM type memory cell’. The chain FeRAM is defined to have a plurality of series-connected memory cells, each of the memory cell is constructed by connecting both electrodes of a ferroelectric capacitor CFE to a source/drain of a MOS transistor, respectively The FeRAM having a plurality of DRAM type memory cells is defined to have a circuit structure of memory cell transistor with a ferroelectric capacitor CFE connected in series to the source of the MOS transistor.
2. Description of the Related Art
In recent years, a FeRAM has been developed because it is nonvolatile and can read/write at a high speed. A FeRAM is characterized in that it is nonvolatile and is read out destructively, or data is destructed during an amount of voltage potential difference is applied between both electrodes of a ferroelectric capacitor.
A chain FeRAM is made up of a plurality of series connected memory cells, each of the memory cells is made by connecting the electrodes of a ferroelectric capacitor to a source and a drain of a MOS transistor, respectively. In order to prevent destruction of stored data due to an application of the voltage potential difference between the source and the drain electrode during a power-on sequence, it is required to apply the word line supply voltage VPP for driving memory cell transistors and then apply other various voltages.
Particularly, if the value of ½·VAA voltage potential, which is applied to bit lines, plate lines, and source, drain, and channel regions of the memory cell array during standby states, increases after the value of VPP potential is stepped up, the value of VPP itself further increases. This results emanates from a large amount of capacitive coupling between the electrode to which the value of VPP voltage potential is applied and the electrode to which the value of ½·VAA voltage potential is applied. Therefore, there is a problem that a high electric field is applied between the gate and source of the memory cell transistor, impairing reliability of the memory cell transistor as a result.
A semiconductor integrated circuit, which includes chain FeRAM cells, a VPP power supply circuit configured to generate the value of VPP power supply voltage supplied to the gate of the memory cell transistor in standby states, and a VAA power supply circuit configured to generate the value of VAA power supply voltage supplied to the source or drain of the memory cell transistor and is operational after the VPP power supply circuit starts working, after the value of the power supply voltage VDD is turned-on, and which is capable of suppressing degradation of data retention characteristics, has been disclosed (see Japanese Patent Application Laid-open No. 2003-196974, for example)